An information processing system generally includes a processor core, a cache memory, and a main memory. The cache memory is configured by a Static Random Access Memory (SRAM), and the main memory is configured by a Dynamic Random Access Memory (DRAM). Both of the SRAM and the DRAM are volatile memories that require a power in order for data retention. The SRAM has a large leakage current in a data cell, and the DRAM requires a rewrite (refresh) operation for data retention. Therefore, both of the SRAM and the DRAM have a problem that power consumption is high.
Accordingly, a method for reducing power consumption has been adopted with respect to an information processing system having a state in which the information processing system executes an operation (hereinafter, referred to as an operation mode) and a state in which the information processing system does not execute an operation (hereinafter, referred to as a standby mode). Specifically, when the information processing system is in the standby mode, since there is no access from the processor core to the cache memory, a power voltage of the SRAM constituting the cache memory is dropped down to a minimum voltage at which data is retainable, or data within the SRAM is stored in the main memory and then power of the SRAM is shut down, thereby reducing power consumption.
As a method reducing power consumption of the information processing system, a method focused on the memories in the processing system consist of nonvolatile memories has been suggested. The system will be less setup time because it does not need to reload data after a standby mode. The longer time in a standby mode will result in reducing power consumption. As a method for further reducing power consumption, the partitioned nonvolatile memory in the processing system has been suggested. For example, in an information processing apparatus including a nonvolatile memory with a plurality of memory arrays, the power supply is controlled at every memory array, such that when the processor accesses specific memory arrays, ON/OFF operations of the power supply for the specific memory arrays, which are to be accessed, are controlled while the power supply for other memory arrays are shut down. In this manner, the low power consumption is realized.